In Hardware Secure Modules (HSM) it is desirable to monitor the integrity of program code or data by an integrity checking circuit which is independent from the central processing unit (CPU) itself. The integrity checking circuit may be implemented in a less tamper prone way than the CPU system. For example the integrity checking circuit may be implemented as hardwired logic. When a change of the memory content is detected, the CPU may be halted, thereby increasing the tamper resistance of the overall system. Furthermore, hardware secure modules may be resistant against side channel attacks by inserting random wait-states into the CPU execution flow. For example, side channel attacks may be executed by monitoring the power supply during operations, e.g. during security related operations. Inserting random wait states into the CPU execution flow may disperse the power profile over time and may remove visible characteristics of security related operations. Random wait-state insertion may be used to prevent side-channel attacks. Both integrity checking and random wait-state insertion may slow down the program execution of the CPU.